1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a dynamic random access memory (DRAM) capacitor structure and its method of fabrication.
2. Description of the Related Art
DRAM is now extensively used in all kinds of integrated circuit devices, and has become an indispensable element to the electronic industries in this information age. FIG. 1 is the circuit diagram of a memory cell or memory unit of a DRAM device. As shown in FIG. 1, the memory cell comprises a pass transistor T and a storage capacitor C. The source terminal of the pass transistor T is connected to a bit line (BL), the drain terminal is connected to a storage electrode 6 of the storage capacitor C, the gate terminal is connected to a word line (WL) and the opposed electrode 8 of the storage capacitor C is connected to a fixed voltage source. Between the storage electrode 6 and the opposed electrode 8, there is a dielectric layer 7. Those who are familiar with the art of semiconductor manufacture may know, the capacitor C is used for storing up digital data, and therefore must have a sufficiently large capacitance to avoid rapid data lost.
In the fabrication of conventional DRAMs having a memory capacity of 1 MB or less, a two dimensional capacitor device, generally known as the planar-type capacitor, is often employed for the storage of digital data. FIG. 2 is a cross-sectional view of a conventional planar-type DRAM capacitor. As shown in FIG. 2, a silicon substrate 10 is first provided. Then, a field oxide layer 11 is formed on the substrate 10 to define the active regions. Next, a gate oxide layer 12, a gate oxide layer 13 and source/drain regions 14 are sequentially formed on the substrate 10 constituting a pass transistor T. In a subsequent step, a dielectric layer 7 and a conducting layer 8 are sequentially formed over portions of the substrate neighboring the drain terminal. The region 6 where the dielectric layer 7 and the conducting layer 8 overlap the substrate 10 forms a storage capacitor C. Quite obvious from the above planar-type capacitor structure, a relatively large surface area is required to form a storage capacitor C that has sufficient capacitance. Hence, this design is unable to meet the demand of ever increasing level of integration for DRAM devices.
In general, highly integrate DRAMs, for example, those bigger than about 4 MB memory capacitor, requires three dimensional capacitor structures such as the stack-type or the trench-type structure for the capacitor devices.
FIG. 3 is a cross-sectional view of a conventional stack- type capacitor structure. As shown in FIG. 3, a field oxide layer 11, a gate oxide layer 12, a gate oxide layer 13 and source/drain regions 14 are sequentially formed above a substrate 10 constituting a pass transistor T. Thereafter, an insulating layer 15 is formed over the substrate 10, then a contact opening 14 is etched out exposing portions of a source/drain region 14. Subsequently, a polysilicon layer 6 (functioning as the storage electrode), a dielectric layer 7 and a conducting layer 8 (functioning as the opposed electrode) are sequentially formed over the contact opening, thus establishing a stack-type DRAM capacitor memory cell. The above stack-type capacitor structure is capable of supplying a sufficiently large amount of capacitance with relatively good device integrity. However, for higher level of integration, such as in a 64 MB or bigger storage capacity DRAM, even a simple stack-type capacitor structure is insufficient.
On the other hand. Another means of increasing the capacitance is to produce a trench-type capacitor. FIG. 4 is a cross-sectional view of a conventional trench-type capacitor structure. As shown in FIG. 4, processes very similar to the fabrication of a stack-type capacitor are first performed forming a pass transistor T over a silicon substrate 10. The pass transistor T includes a gate oxide layer 12, a gate oxide layer 13 and a source/drain region 14. A deep trench is formed by etching the substrate 10 neighboring a grain terminal 14, and then a storage capacitor C is formed inside the trench region. The storage capacitor C is formed on the side walls of the trench and comprises a storage electrode 6, a dielectric layer 7 and a polysilicon opposed electrode 8. The above trench-type capacitor is also capable of increasing the surface area of the electrode and hence increasing capacitance. However, etching the substrate 10 to form a trench may cause some damages to the crystal lattice, and leakage may increase as a result, thereby affecting the operational characteristics of the device. In addition, as the aspect ratio of the trench is increased, the etching rate will correspondingly be reduced. And therefore, fabrication becomes more difficult and productivity is certain to be affected.
In light of the foregoing, there is a need for increasing the capacitance in a DRAM capacitor.